Environment Settings | ||||
Environment Variable | xst | ngdbuild | map | par |
PATHEXT | .COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH; .MSC |
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Path | D:\Xilinx\ISE_DS\ISE\\lib\nt; D:\Xilinx\ISE_DS\ISE\\bin\nt; D:\Xilinx\ISE_DS\PlanAhead\bin; D:\Xilinx\ISE_DS\ISE\bin\nt; D:\Xilinx\ISE_DS\ISE\lib\nt; D:\Xilinx\ISE_DS\EDK\bin\nt; D:\Xilinx\ISE_DS\EDK\lib\nt; D:\Xilinx\ISE_DS\EDK\gnu\microblaze\nt\bin; D:\Xilinx\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin; D:\Xilinx\ISE_DS\EDK\gnuwin\bin; D:\Xilinx\ISE_DS\common\bin\nt; D:\Xilinx\ISE_DS\common\lib\nt; C:\Windows\system32; C:\Windows; C:\Windows\System32\Wbem; C:\Windows\System32\WindowsPowerShell\v1.0\; C:\Program Files\ATI Technologies\ATI.ACE\Core-Static; D:\Matlab\runtime\win32; D:\Matlab\bin; D:\Altium Designer\System; d:\altera\quartus\bin; C:\Program Files\QuickTime Alternative\QTSystem; D:\WDK\bin; D:\cc65\bin; D:\Atmel\Flip 3.4.2\bin |
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XILINX | D:\Xilinx\ISE_DS\ISE\ | < data not available > | < data not available > | < data not available > |
XILINXD_LICENSE_FILE | d:\Xilinx\xilinx_ise.lic | < data not available > | < data not available > | < data not available > |
XILINX_DSP | D:\Xilinx\ISE_DS\ISE | < data not available > | < data not available > | < data not available > |
XILINX_EDK | D:\Xilinx\ISE_DS\EDK | < data not available > | < data not available > | < data not available > |
XILINX_PLANAHEAD | D:\Xilinx\ISE_DS\PlanAhead | < data not available > | < data not available > | < data not available > |
Synthesis Property Settings | |||
Switch Name | Property Name | Value | Default Value |
-ifn | display.prj | ||
-ifmt | mixed | MIXED | |
-ofn | display | ||
-ofmt | NGC | NGC | |
-p | xc3s250e-4-tq144 | ||
-top | display | ||
-opt_mode | Optimization Goal | Speed | SPEED |
-opt_level | Optimization Effort | 1 | 1 |
-iuc | Use synthesis Constraints File | NO | NO |
-keep_hierarchy | Keep Hierarchy | No | NO |
-netlist_hierarchy | Netlist Hierarchy | As_Optimized | as_optimized |
-rtlview | Generate RTL Schematic | Yes | NO |
-glob_opt | Global Optimization Goal | AllClockNets | ALLCLOCKNETS |
-read_cores | Read Cores | YES | YES |
-write_timing_constraints | Write Timing Constraints | NO | NO |
-cross_clock_analysis | Cross Clock Analysis | NO | NO |
-bus_delimiter | Bus Delimiter | <> | <> |
-slice_utilization_ratio | Slice Utilization Ratio | 100 | 100% |
-bram_utilization_ratio | BRAM Utilization Ratio | 100 | 100% |
-verilog2001 | Verilog 2001 | YES | YES |
-fsm_extract | YES | YES | |
-fsm_encoding | Auto | AUTO | |
-safe_implementation | No | NO | |
-fsm_style | LUT | LUT | |
-ram_extract | Yes | YES | |
-ram_style | Auto | AUTO | |
-rom_extract | Yes | YES | |
-shreg_extract | YES | YES | |
-rom_style | Auto | AUTO | |
-auto_bram_packing | NO | NO | |
-resource_sharing | YES | YES | |
-async_to_sync | NO | NO | |
-mult_style | Auto | AUTO | |
-iobuf | YES | YES | |
-max_fanout | 500 | 500 | |
-bufg | 24 | 24 | |
-register_duplication | YES | YES | |
-register_balancing | No | NO | |
-optimize_primitives | NO | NO | |
-use_clock_enable | Yes | YES | |
-use_sync_set | Yes | YES | |
-use_sync_reset | Yes | YES | |
-iob | Auto | AUTO | |
-equivalent_register_removal | YES | YES | |
-slice_utilization_ratio_maxmargin | 5 | 0% |
Operating System Information | ||||
Operating System Information | xst | ngdbuild | map | par |
CPU Architecture/Speed | Intel(R) Core(TM) i3 CPU 530 @ 2.93GHz/2942 MHz | < data not available > | < data not available > | < data not available > |
Host | rtpc | < data not available > | < data not available > | < data not available > |
OS Name | Microsoft Windows 7 , 32-bit | < data not available > | < data not available > | < data not available > |
OS Release | major release (build 7600) | < data not available > | < data not available > | < data not available > |