Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:13.1 (WebPack) - O.40d Target Family: Spartan3E
OS Platform: NT Target Device: xc3s250e
Project ID (random number) dd8f9b87039a4b22ad5d22f643b5434c.7FB1BD9B0FF148949D5380BF999EAA27.4 Target Package: tq144
Registration ID __0_0_0 Target Speed: -4
Date Generated 2011-05-15T02:51:55 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 32-bit OS Release major release (build 7600)
CPU Name Intel(R) Core(TM) i3 CPU 530 @ 2.93GHz CPU Speed 2942 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=1
  • 9-bit addsub=1
Counters=3
  • 14-bit up counter=1
  • 4-bit up counter=1
  • 8-bit up counter=1
FSMs=1 Multiplexers=4
  • 8-bit 4-to-1 multiplexer=2
  • 9-bit 4-to-1 multiplexer=2
RAMs=4
  • 128x8-bit single-port distributed RAM=1
  • 16x8-bit dual-port distributed RAM=2
  • 256x16-bit dual-port distributed RAM=1
ROMs=1
  • 16x4-bit ROM=1
Registers=70
  • Flip-Flops=70
Xors=1
  • 8-bit xor2=1
MiscellaneousStatistics
  • AGG_BONDED_IO=41
  • AGG_IO=41
  • AGG_SLICE=577
  • NUM_4_INPUT_LUT=1088
  • NUM_BONDED_IBUF=16
  • NUM_BONDED_IOB=25
  • NUM_BSCAN=1
  • NUM_BUFGMUX=4
  • NUM_CYMUX=28
  • NUM_DP_RAM=544
  • NUM_LUT_RT=19
  • NUM_RAM32=64
  • NUM_SLICEL=241
  • NUM_SLICEM=336
  • NUM_SLICE_FF=119
  • NUM_XOR=31
NetStatistics
  • NumNets_Active=860
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_CLKPIN=380
  • NumNodesOfType_Active_CNTRLPIN=376
  • NumNodesOfType_Active_DOUBLE=4305
  • NumNodesOfType_Active_DUMMY=4049
  • NumNodesOfType_Active_DUMMYESC=16
  • NumNodesOfType_Active_GLOBAL=177
  • NumNodesOfType_Active_HFULLHEX=66
  • NumNodesOfType_Active_HLONG=3
  • NumNodesOfType_Active_HUNIHEX=245
  • NumNodesOfType_Active_INPUT=4736
  • NumNodesOfType_Active_IOBOUTPUT=16
  • NumNodesOfType_Active_OMUX=665
  • NumNodesOfType_Active_OUTPUT=803
  • NumNodesOfType_Active_PREBXBY=1514
  • NumNodesOfType_Active_VFULLHEX=143
  • NumNodesOfType_Active_VLONG=37
  • NumNodesOfType_Active_VUNIHEX=216
  • NumNodesOfType_Gnd_DOUBLE=3
  • NumNodesOfType_Gnd_DUMMY=2
  • NumNodesOfType_Gnd_INPUT=4
  • NumNodesOfType_Gnd_OMUX=3
  • NumNodesOfType_Gnd_OUTPUT=3
  • NumNodesOfType_Gnd_PREBXBY=3
SiteStatistics
  • IBUF-DIFFMI=3
  • IBUF-DIFFSI=3
  • IOB-DIFFM=11
  • IOB-DIFFS=12
  • SLICEL-SLICEM=87
SiteSummary
  • BSCAN=1
  • BSCAN_BSCAN_BLACKBOX=1
  • BUFGMUX=4
  • BUFGMUX_GCLKMUX=4
  • BUFGMUX_GCLK_BUFFER=4
  • IBUF=16
  • IBUF_INBUF=16
  • IBUF_PAD=16
  • IOB=25
  • IOB_OUTBUF=25
  • IOB_PAD=25
  • SLICEL=241
  • SLICEL_C1VDD=1
  • SLICEL_CYMUXF=15
  • SLICEL_CYMUXG=13
  • SLICEL_F=214
  • SLICEL_F5MUX=79
  • SLICEL_F6MUX=18
  • SLICEL_FFX=50
  • SLICEL_FFY=53
  • SLICEL_G=202
  • SLICEL_GNDF=10
  • SLICEL_GNDG=9
  • SLICEL_XORF=16
  • SLICEL_XORG=15
  • SLICEM=336
  • SLICEM_F=336
  • SLICEM_F5MUX=64
  • SLICEM_F6MUX=32
  • SLICEM_FFY=16
  • SLICEM_G=336
  • SLICEM_WSGEN=304
 
Configuration Data
BUFGMUX
  • S=[S_INV:4] [S:0]
BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:4]
  • S=[S_INV:4] [S:0]
IBUF_PAD
  • IOATTRBOX=[LVCMOS25:16]
  • PULL=[PULLDOWN:2]
IOB
  • O1=[O1_INV:0] [O1:25]
IOB_OUTBUF
  • IN=[IN_INV:0] [IN:25]
IOB_PAD
  • DRIVEATTRBOX=[12:25]
  • IOATTRBOX=[LVCMOS25:25]
  • SLEW=[SLOW:25]
SLICEL
  • BX=[BX_INV:1] [BX:108]
  • BY=[BY:49] [BY_INV:0]
  • CE=[CE:18] [CE_INV:0]
  • CIN=[CIN_INV:0] [CIN:13]
  • CLK=[CLK:60] [CLK_INV:0]
  • SR=[SR:38] [SR_INV:0]
SLICEL_CYMUXF
  • 0=[0:15] [0_INV:0]
  • 1=[1_INV:0] [1:15]
SLICEL_CYMUXG
  • 0=[0:13] [0_INV:0]
SLICEL_F5MUX
  • S0=[S0:79] [S0_INV:0]
SLICEL_F6MUX
  • S0=[S0:18] [S0_INV:0]
SLICEL_FFX
  • CE=[CE:14] [CE_INV:0]
  • CK=[CK:50] [CK_INV:0]
  • D=[D:49] [D_INV:1]
  • FFX_INIT_ATTR=[INIT0:50]
  • FFX_SR_ATTR=[SRLOW:50]
  • LATCH_OR_FF=[FF:50]
  • SR=[SR:32] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:37] [SYNC:13]
SLICEL_FFY
  • CE=[CE:16] [CE_INV:0]
  • CK=[CK:53] [CK_INV:0]
  • D=[D:53] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:52] [INIT1:1]
  • FFY_SR_ATTR=[SRLOW:52] [SRHIGH:1]
  • LATCH_OR_FF=[FF:53]
  • SR=[SR:33] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:40] [SYNC:13]
SLICEL_XORF
  • 1=[1_INV:0] [1:16]
SLICEM
  • BX=[BX_INV:0] [BX:64]
  • BY=[BY:336] [BY_INV:0]
  • CE=[CE:16] [CE_INV:0]
  • CLK=[CLK:320] [CLK_INV:0]
  • SR=[SR:304] [SR_INV:0]
SLICEM_F
  • DI=[DI:304] [DI_INV:0]
  • F_ATTR=[DUAL_PORT:272]
  • LUT_OR_MEM=[LUT:32] [RAM:304]
SLICEM_F5MUX
  • S0=[S0:64] [S0_INV:0]
SLICEM_F6MUX
  • S0=[S0:32] [S0_INV:0]
SLICEM_FFY
  • CE=[CE:16] [CE_INV:0]
  • CK=[CK:16] [CK_INV:0]
  • D=[D:16] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:16]
  • FFY_SR_ATTR=[SRLOW:16]
  • LATCH_OR_FF=[FF:16]
  • SYNC_ATTR=[ASYNC:16]
SLICEM_G
  • DI=[DI:304] [DI_INV:0]
  • G_ATTR=[DUAL_PORT:272]
  • LUT_OR_MEM=[LUT:32] [RAM:304]
SLICEM_WSGEN
  • CK=[CK:304] [CK_INV:0]
  • WE=[WE_INV:0] [WE:304]
  • WE0=[WE0:32] [WE0_INV:0]
 
Pin Data
BSCAN
  • DRCK1=1
  • SEL1=1
  • TDI=1
  • TDO1=1
  • TDO2=1
  • UPDATE=1
BSCAN_BSCAN_BLACKBOX
  • DRCK1=1
  • SEL1=1
  • TDI=1
  • TDO1=1
  • TDO2=1
  • UPDATE=1
BUFGMUX
  • I0=4
  • O=4
  • S=4
BUFGMUX_GCLKMUX
  • I0=4
  • OUT=4
  • S=4
BUFGMUX_GCLK_BUFFER
  • IN=4
  • OUT=4
IBUF
  • I=16
  • PAD=16
IBUF_INBUF
  • IN=16
  • OUT=16
IBUF_PAD
  • PAD=16
IOB
  • O1=25
  • PAD=25
IOB_OUTBUF
  • IN=25
  • OUT=25
IOB_PAD
  • PAD=25
SLICEL
  • BX=109
  • BY=49
  • CE=18
  • CIN=13
  • CLK=60
  • COUT=13
  • F1=214
  • F2=201
  • F3=187
  • F4=114
  • F5=36
  • FX=16
  • FXINA=18
  • FXINB=18
  • G1=202
  • G2=195
  • G3=180
  • G4=122
  • SR=38
  • X=154
  • XQ=50
  • Y=105
  • YQ=53
SLICEL_C1VDD
  • 1=1
SLICEL_CYMUXF
  • 0=15
  • 1=15
  • OUT=15
  • S0=15
SLICEL_CYMUXG
  • 0=13
  • 1=13
  • OUT=13
  • S0=13
SLICEL_F
  • A1=214
  • A2=201
  • A3=187
  • A4=114
  • D=214
SLICEL_F5MUX
  • F=79
  • G=79
  • OUT=79
  • S0=79
SLICEL_F6MUX
  • 0=18
  • 1=18
  • OUT=18
  • S0=18
SLICEL_FFX
  • CE=14
  • CK=50
  • D=50
  • Q=50
  • SR=32
SLICEL_FFY
  • CE=16
  • CK=53
  • D=53
  • Q=53
  • SR=33
SLICEL_G
  • A1=202
  • A2=195
  • A3=180
  • A4=122
  • D=202
SLICEL_GNDF
  • 0=10
SLICEL_GNDG
  • 0=9
SLICEL_XORF
  • 0=16
  • 1=16
  • O=16
SLICEL_XORG
  • 0=15
  • 1=15
  • O=15
SLICEM
  • BX=64
  • BY=336
  • CE=16
  • CLK=320
  • F1=336
  • F2=336
  • F3=336
  • F4=304
  • F5=32
  • FX=16
  • FXINA=32
  • FXINB=32
  • G1=336
  • G2=336
  • G3=336
  • G4=304
  • SR=304
  • X=304
  • YQ=16
SLICEM_F
  • A1=336
  • A2=336
  • A3=336
  • A4=304
  • D=336
  • DI=304
  • WF1=304
  • WF2=304
  • WF3=304
  • WF4=304
  • WS=304
SLICEM_F5MUX
  • F=64
  • G=64
  • OUT=64
  • S0=64
SLICEM_F6MUX
  • 0=32
  • 1=32
  • OUT=32
  • S0=32
SLICEM_FFY
  • CE=16
  • CK=16
  • D=16
  • Q=16
SLICEM_G
  • A1=336
  • A2=336
  • A3=336
  • A4=304
  • D=64
  • DI=304
  • WG1=304
  • WG2=304
  • WG3=304
  • WG4=304
  • WS=304
SLICEM_WSGEN
  • CK=304
  • WE=304
  • WE0=32
  • WSF=304
  • WSG=304
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-tq144-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s250e-tq144-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-tq144-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s250e-tq144-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-tq144-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s250e-tq144-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-tq144-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s250e-tq144-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
XSLTProcess 2 2 0 0 0 0 0
_impact 79 79 0 0 0 0 0
bitgen 54 54 0 0 0 0 0
bitinit 6 6 0 0 0 0 0
cpldfit 2 2 0 0 0 0 0
cse_server 6 3 0 0 0 0 0
elfcheck 23 23 0 0 0 0 0
hprep6 1 1 0 0 0 0 0
libgen 4 4 0 0 0 0 0
map 54 54 0 0 0 0 0
netgen 5 5 0 0 0 0 0
ngcbuild 57 57 0 0 0 0 0
ngdbuild 56 56 0 0 0 0 0
obngc 2 2 0 0 0 0 0
par 54 54 0 0 0 0 0
partgen 26 25 0 0 0 0 0
platgen 13 12 0 0 0 0 0
psf2Edward 4 4 0 0 0 0 0
taengine 1 1 0 0 0 0 0
trce 53 53 0 0 0 0 0
tsim 1 1 0 0 0 0 0
xdsgen 4 4 0 0 0 0 0
xps 22 22 0 0 0 0 0
xst 258 258 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/platform_studio/ps_c_ipw_configuring_fifos.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2011-05-08T06:27:41
PROP_intWbtProjectID=7FB1BD9B0FF148949D5380BF999EAA27 PROP_intWbtProjectIteration=4
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_AutoTop=false PROP_DevFamily=Spartan3E
PROP_DevDevice=xc3s250e PROP_DevFamilyPMName=spartan3e
PROP_DevPackage=tq144 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-4 PROP_PreferredLanguage=Verilog
FILE_UCF=1 FILE_VERILOG=11
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=2 NGDBUILD_NUM_BUFGP=2 NGDBUILD_NUM_FD=28 NGDBUILD_NUM_FDC=30
NGDBUILD_NUM_FDCE=8 NGDBUILD_NUM_FDE=26 NGDBUILD_NUM_FDP=1 NGDBUILD_NUM_FDR=14
NGDBUILD_NUM_FDRE=12 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=14 NGDBUILD_NUM_INV=2
NGDBUILD_NUM_LUT1=14 NGDBUILD_NUM_LUT2=28 NGDBUILD_NUM_LUT2_L=1 NGDBUILD_NUM_LUT3=194
NGDBUILD_NUM_LUT3_L=1 NGDBUILD_NUM_LUT4=221 NGDBUILD_NUM_LUT4_D=5 NGDBUILD_NUM_LUT4_L=10
NGDBUILD_NUM_MUXCY=28 NGDBUILD_NUM_MUXF5=111 NGDBUILD_NUM_MUXF6=34 NGDBUILD_NUM_MUXF7=16
NGDBUILD_NUM_OBUF=25 NGDBUILD_NUM_RAM16X1D=272 NGDBUILD_NUM_RAM32X1S=32 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=31
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BSCAN_SPARTAN3=1 NGDBUILD_NUM_BUFG=4 NGDBUILD_NUM_FD=28 NGDBUILD_NUM_FDC=30
NGDBUILD_NUM_FDCE=8 NGDBUILD_NUM_FDE=26 NGDBUILD_NUM_FDP=1 NGDBUILD_NUM_FDR=14
NGDBUILD_NUM_FDRE=12 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=14 NGDBUILD_NUM_IBUFG=2
NGDBUILD_NUM_INV=2 NGDBUILD_NUM_LUT1=14 NGDBUILD_NUM_LUT2=28 NGDBUILD_NUM_LUT2_L=1
NGDBUILD_NUM_LUT3=194 NGDBUILD_NUM_LUT3_L=1 NGDBUILD_NUM_LUT4=221 NGDBUILD_NUM_LUT4_D=5
NGDBUILD_NUM_LUT4_L=10 NGDBUILD_NUM_MUXCY=28 NGDBUILD_NUM_MUXF5=111 NGDBUILD_NUM_MUXF6=34
NGDBUILD_NUM_MUXF7=16 NGDBUILD_NUM_OBUF=25 NGDBUILD_NUM_PULLDOWN=2 NGDBUILD_NUM_RAM32X1S=32
NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=31