debug_module Project Status
Project File: MiniRISC_System.xise Parser Errors: No Errors
Module Name: debug_module Implementation State: Synthesized
Target Device: xc3s250e-4tq144
  • Errors:
No Errors
Product Version:ISE 14.4
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slices 82 2448 3%
Number of Slice Flip Flops 100 4896 2%
Number of 4 input LUTs 136 4896 2%
Number of bonded IOBs 90 108 83%
Number of GCLKs 1 24 4%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentK jan. 22 00:36:47 2013001 Info (0 new)
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 01/22/2013 - 00:41:31