debug_module Project Status | |||
Project File: | MiniRISC_System.xise | Parser Errors: | No Errors |
Module Name: | debug_module | Implementation State: | Synthesized |
Target Device: | xc3s250e-4tq144 |
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No Errors |
Product Version: | ISE 14.4 |
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No Warnings |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slices | 82 | 2448 | 3% | |
Number of Slice Flip Flops | 100 | 4896 | 2% | |
Number of 4 input LUTs | 136 | 4896 | 2% | |
Number of bonded IOBs | 90 | 108 | 83% | |
Number of GCLKs | 1 | 24 | 4% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | K jan. 22 00:36:47 2013 | 0 | 0 | 1 Info (0 new) | |
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated |