Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.6 (WebPack) - P.68d Target Family: Spartan3E
OS Platform: NT Target Device: xc3s250e
Project ID (random number) 52fbe264b4d648dba7836b1042915ff7.314A0CF2C5504D1492F1C1F4C1B6F4E4.3 Target Package: tq144
Registration ID __0_0_0 Target Speed: -4
Date Generated 2014-09-25T16:04:36 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 32-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i3 CPU 550 @ 3.20GHz CPU Speed 3192 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=7
  • 16-bit subtractor=1
  • 4-bit subtractor=1
  • 8-bit adder=3
  • 8-bit subtractor=1
  • 9-bit adder carry in=1
Comparators=2
  • 8-bit comparator equal=2
Counters=18
  • 10-bit up counter=1
  • 15-bit up counter=1
  • 17-bit down counter=1
  • 32-bit up counter=2
  • 4-bit up counter=3
  • 4-bit updown counter=4
  • 5-bit up counter=1
  • 6-bit up counter=1
  • 8-bit down counter=1
  • 8-bit up counter=2
  • 9-bit up counter=1
FSMs=3 Multiplexers=97
  • 1-bit 12-to-1 multiplexer=1
  • 1-bit 2-to-1 multiplexer=24
  • 1-bit 5-to-1 multiplexer=2
  • 1-bit 7-to-1 multiplexer=6
  • 1-bit 8-to-1 multiplexer=8
  • 11-bit 2-to-1 multiplexer=2
  • 16-bit 2-to-1 multiplexer=4
  • 28-bit 2-to-1 multiplexer=1
  • 3-bit 2-to-1 multiplexer=1
  • 3-bit 4-to-1 multiplexer=2
  • 4-bit 2-to-1 multiplexer=3
  • 6-bit 2-to-1 multiplexer=2
  • 8-bit 2-to-1 multiplexer=26
  • 8-bit 4-to-1 multiplexer=3
  • 9-bit 2-to-1 multiplexer=4
  • 9-bit 4-to-1 multiplexer=8
RAMs=9
  • 128x8-bit single-port distributed RAM=1
  • 16384x1-bit single-port block Read Only RAM=1
  • 16x14-bit dual-port distributed RAM=1
  • 16x8-bit dual-port distributed RAM=2
  • 2048x8-bit single-port block Read Only RAM=1
  • 256x1-bit dual-port distributed RAM=1
  • 256x16-bit dual-port distributed RAM=1
  • 8x16-bit single-port distributed Read Only RAM=1
Registers=471
  • Flip-Flops=471
Shift Registers=25
  • 16-bit dynamic shift register=25
Xors=6
  • 1-bit xor2=2
  • 1-bit xor9=1
  • 8-bit xor2=3
MiscellaneousStatistics
  • AGG_BONDED_IO=68
  • AGG_IO=68
  • AGG_SLICE=1414
  • NUM_4_INPUT_LUT=2432
  • NUM_BONDED_IBUF=20
  • NUM_BONDED_IOB=48
  • NUM_BSCAN=1
  • NUM_BUFGMUX=1
  • NUM_CYMUX=158
  • NUM_DP_RAM=604
  • NUM_LUT_RT=111
  • NUM_RAM32=64
  • NUM_RAMB16=10
  • NUM_SHIFT=29
  • NUM_SLICEL=1029
  • NUM_SLICEM=385
  • NUM_SLICE_FF=641
  • NUM_XOR=163
NetStatistics
  • NumNets_Active=2648
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BRAMADDR=201
  • NumNodesOfType_Active_BRAMDUMMY=233
  • NumNodesOfType_Active_CLKPIN=774
  • NumNodesOfType_Active_CNTRLPIN=937
  • NumNodesOfType_Active_DOUBLE=8684
  • NumNodesOfType_Active_DUMMY=8325
  • NumNodesOfType_Active_DUMMYBANK=160
  • NumNodesOfType_Active_DUMMYESC=42
  • NumNodesOfType_Active_GLOBAL=181
  • NumNodesOfType_Active_HFULLHEX=115
  • NumNodesOfType_Active_HLONG=16
  • NumNodesOfType_Active_HUNIHEX=642
  • NumNodesOfType_Active_INPUT=9941
  • NumNodesOfType_Active_IOBOUTPUT=42
  • NumNodesOfType_Active_OMUX=2240
  • NumNodesOfType_Active_OUTPUT=2386
  • NumNodesOfType_Active_PREBXBY=2739
  • NumNodesOfType_Active_VFULLHEX=450
  • NumNodesOfType_Active_VLONG=90
  • NumNodesOfType_Active_VUNIHEX=697
  • NumNodesOfType_Gnd_BRAMDUMMY=28
  • NumNodesOfType_Gnd_DOUBLE=24
  • NumNodesOfType_Gnd_DUMMY=14
  • NumNodesOfType_Gnd_INPUT=57
  • NumNodesOfType_Gnd_OMUX=31
  • NumNodesOfType_Gnd_OUTPUT=26
  • NumNodesOfType_Gnd_PREBXBY=16
  • NumNodesOfType_Gnd_VFULLHEX=2
  • NumNodesOfType_Gnd_VUNIHEX=1
SiteStatistics
  • IBUF-DIFFMI=2
  • IBUF-DIFFSI=4
  • IOB-DIFFM=22
  • IOB-DIFFS=22
  • SLICEL-SLICEM=393
SiteSummary
  • BSCAN=1
  • BSCAN_BSCAN_BLACKBOX=1
  • BUFGMUX=1
  • BUFGMUX_GCLKMUX=1
  • BUFGMUX_GCLK_BUFFER=1
  • IBUF=20
  • IBUF_INBUF=20
  • IBUF_PAD=20
  • IOB=48
  • IOB_INBUF=22
  • IOB_OUTBUF=48
  • IOB_PAD=48
  • RAMB16=10
  • RAMB16_RAMB16=10
  • RAMB16_RAMB16A=10
  • RAMB16_RAMB16B=8
  • SLICEL=1029
  • SLICEL_C1VDD=24
  • SLICEL_C2VDD=18
  • SLICEL_CYMUXF=83
  • SLICEL_CYMUXG=75
  • SLICEL_F=841
  • SLICEL_F5MUX=160
  • SLICEL_F6MUX=27
  • SLICEL_FFX=321
  • SLICEL_FFY=292
  • SLICEL_G=826
  • SLICEL_GNDF=55
  • SLICEL_GNDG=53
  • SLICEL_XORF=83
  • SLICEL_XORG=80
  • SLICEM=385
  • SLICEM_F=380
  • SLICEM_F5MUX=66
  • SLICEM_F6MUX=34
  • SLICEM_FFX=1
  • SLICEM_FFY=27
  • SLICEM_G=385
  • SLICEM_WSGEN=351
 
Configuration Data
BUFGMUX
  • S=[S_INV:1] [S:0]
BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:1]
  • S=[S_INV:1] [S:0]
IBUF_PAD
  • IOATTRBOX=[LVCMOS25:20]
  • PULL=[PULLDOWN:5]
IOB
  • O1=[O1_INV:17] [O1:31]
  • T1=[T1_INV:11] [T1:11]
IOB_OUTBUF
  • IN=[IN_INV:17] [IN:31]
  • TRI=[TRI_INV:11] [TRI:11]
IOB_PAD
  • DRIVEATTRBOX=[12:48]
  • IOATTRBOX=[LVCMOS25:48]
  • PULL=[PULLDOWN:22]
  • SLEW=[SLOW:48]
RAMB16
  • CLKA=[CLKA_INV:0] [CLKA:10]
  • CLKB=[CLKB_INV:0] [CLKB:8]
  • ENA=[ENA_INV:0] [ENA:10]
  • ENB=[ENB_INV:0] [ENB:8]
  • SSRA=[SSRA_INV:0] [SSRA:10]
  • SSRB=[SSRB_INV:0] [SSRB:8]
  • WEA=[WEA:10] [WEA_INV:0]
  • WEB=[WEB:8] [WEB_INV:0]
RAMB16_RAMB16A
  • CLKA=[CLKA_INV:0] [CLKA:10]
  • ENA=[ENA_INV:0] [ENA:10]
  • PORTA_ATTR=[16384X1:1] [2048X9:9]
  • SSRA=[SSRA_INV:0] [SSRA:10]
  • WEA=[WEA:10] [WEA_INV:0]
  • WRITEMODEA=[WRITE_FIRST:10]
RAMB16_RAMB16B
  • CLKB=[CLKB_INV:0] [CLKB:8]
  • ENB=[ENB_INV:0] [ENB:8]
  • PORTB_ATTR=[2048X9:8]
  • SSRB=[SSRB_INV:0] [SSRB:8]
  • WEB=[WEB:8] [WEB_INV:0]
  • WRITEMODEB=[WRITE_FIRST:8]
SLICEL
  • BX=[BX_INV:6] [BX:302]
  • BY=[BY:192] [BY_INV:1]
  • CE=[CE:267] [CE_INV:3]
  • CIN=[CIN_INV:0] [CIN:74]
  • CLK=[CLK:389] [CLK_INV:0]
  • SR=[SR:270] [SR_INV:1]
SLICEL_CYMUXF
  • 0=[0:83] [0_INV:0]
  • 1=[1_INV:0] [1:83]
SLICEL_CYMUXG
  • 0=[0:75] [0_INV:0]
SLICEL_F5MUX
  • S0=[S0:160] [S0_INV:0]
SLICEL_F6MUX
  • S0=[S0:27] [S0_INV:0]
SLICEL_FFX
  • CE=[CE:224] [CE_INV:3]
  • CK=[CK:321] [CK_INV:0]
  • D=[D:315] [D_INV:6]
  • FFX_INIT_ATTR=[INIT0:299] [INIT1:22]
  • FFX_SR_ATTR=[SRLOW:299] [SRHIGH:22]
  • LATCH_OR_FF=[FF:321]
  • REV=[REV_INV:0] [REV:20]
  • SR=[SR:218] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:109] [SYNC:212]
SLICEL_FFY
  • CE=[CE:205] [CE_INV:2]
  • CK=[CK:292] [CK_INV:0]
  • D=[D:291] [D_INV:1]
  • FFY_INIT_ATTR=[INIT0:265] [INIT1:27]
  • FFY_SR_ATTR=[SRLOW:265] [SRHIGH:27]
  • LATCH_OR_FF=[FF:292]
  • REV=[REV_INV:0] [REV:1]
  • SR=[SR:198] [SR_INV:1]
  • SYNC_ATTR=[ASYNC:108] [SYNC:184]
SLICEL_XORF
  • 1=[1_INV:0] [1:83]
SLICEM
  • BX=[BX_INV:0] [BX:79]
  • BY=[BY:385] [BY_INV:0]
  • CE=[CE:25] [CE_INV:0]
  • CLK=[CLK:367] [CLK_INV:0]
  • SR=[SR:351] [SR_INV:0]
SLICEM_F
  • DI=[DI:346] [DI_INV:0]
  • F_ATTR=[DUAL_PORT:302] [SHIFT_REG:12]
  • LUT_OR_MEM=[LUT:34] [RAM:346]
SLICEM_F5MUX
  • S0=[S0:66] [S0_INV:0]
SLICEM_F6MUX
  • S0=[S0:34] [S0_INV:0]
SLICEM_FFX
  • CE=[CE:1] [CE_INV:0]
  • CK=[CK:1] [CK_INV:0]
  • D=[D:1] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:1]
  • FFX_SR_ATTR=[SRLOW:1]
  • LATCH_OR_FF=[FF:1]
  • SYNC_ATTR=[ASYNC:1]
SLICEM_FFY
  • CE=[CE:25] [CE_INV:0]
  • CK=[CK:27] [CK_INV:0]
  • D=[D:27] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:27]
  • FFY_SR_ATTR=[SRLOW:27]
  • LATCH_OR_FF=[FF:27]
  • SYNC_ATTR=[ASYNC:27]
SLICEM_G
  • DI=[DI:351] [DI_INV:0]
  • G_ATTR=[DUAL_PORT:302] [SHIFT_REG:17]
  • LUT_OR_MEM=[LUT:34] [RAM:351]
SLICEM_WSGEN
  • CK=[CK:351] [CK_INV:0]
  • SYNC_ATTR=[ASYNC:11]
  • WE=[WE_INV:0] [WE:351]
  • WE0=[WE0:32] [WE0_INV:0]
 
Pin Data
BSCAN
  • CAPTURE=1
  • DRCK1=1
  • SEL1=1
  • SHIFT=1
  • TDI=1
  • TDO1=1
  • TDO2=1
  • UPDATE=1
BSCAN_BSCAN_BLACKBOX
  • CAPTURE=1
  • DRCK1=1
  • SEL1=1
  • SHIFT=1
  • TDI=1
  • TDO1=1
  • TDO2=1
  • UPDATE=1
BUFGMUX
  • I0=1
  • O=1
  • S=1
BUFGMUX_GCLKMUX
  • I0=1
  • OUT=1
  • S=1
BUFGMUX_GCLK_BUFFER
  • IN=1
  • OUT=1
IBUF
  • I=20
  • PAD=20
IBUF_INBUF
  • IN=20
  • OUT=20
IBUF_PAD
  • PAD=20
IOB
  • I=22
  • O1=48
  • PAD=48
  • T1=22
IOB_INBUF
  • IN=22
  • OUT=22
IOB_OUTBUF
  • IN=48
  • OUT=48
  • TRI=22
IOB_PAD
  • PAD=48
RAMB16
  • ADDRA0=1
  • ADDRA1=1
  • ADDRA10=10
  • ADDRA11=10
  • ADDRA12=10
  • ADDRA13=10
  • ADDRA2=1
  • ADDRA3=10
  • ADDRA4=10
  • ADDRA5=10
  • ADDRA6=10
  • ADDRA7=10
  • ADDRA8=10
  • ADDRA9=10
  • ADDRB10=8
  • ADDRB11=8
  • ADDRB12=8
  • ADDRB13=8
  • ADDRB3=8
  • ADDRB4=8
  • ADDRB5=8
  • ADDRB6=8
  • ADDRB7=8
  • ADDRB8=8
  • ADDRB9=8
  • CLKA=10
  • CLKB=8
  • DIA0=8
  • DIA1=8
  • DIA2=8
  • DIA3=8
  • DIA4=8
  • DIA5=8
  • DIA6=8
  • DIA7=8
  • DIPA0=8
  • DOA0=10
  • DOA1=9
  • DOA2=9
  • DOA3=9
  • DOA4=9
  • DOA5=9
  • DOA6=9
  • DOA7=9
  • DOB0=8
  • DOB1=8
  • DOB2=8
  • DOB3=8
  • DOB4=8
  • DOB5=8
  • DOB6=8
  • DOB7=8
  • DOPA0=8
  • DOPB0=8
  • ENA=10
  • ENB=8
  • SSRA=10
  • SSRB=8
  • WEA=10
  • WEB=8
RAMB16_RAMB16
  • ADDRA=10
  • ADDRB=8
  • DIA=10
  • DIB=8
  • DOA=10
  • DOB=8
RAMB16_RAMB16A
  • ADDRA=10
  • ADDRA0=1
  • ADDRA1=1
  • ADDRA10=10
  • ADDRA11=10
  • ADDRA12=10
  • ADDRA13=10
  • ADDRA2=1
  • ADDRA3=10
  • ADDRA4=10
  • ADDRA5=10
  • ADDRA6=10
  • ADDRA7=10
  • ADDRA8=10
  • ADDRA9=10
  • CLKA=10
  • DIA=10
  • DIA0=8
  • DIA1=8
  • DIA2=8
  • DIA3=8
  • DIA4=8
  • DIA5=8
  • DIA6=8
  • DIA7=8
  • DIPA0=8
  • DOA=10
  • DOA0=10
  • DOA1=9
  • DOA2=9
  • DOA3=9
  • DOA4=9
  • DOA5=9
  • DOA6=9
  • DOA7=9
  • DOPA0=8
  • ENA=10
  • SSRA=10
  • WEA=10
RAMB16_RAMB16B
  • ADDRB=8
  • ADDRB10=8
  • ADDRB11=8
  • ADDRB12=8
  • ADDRB13=8
  • ADDRB3=8
  • ADDRB4=8
  • ADDRB5=8
  • ADDRB6=8
  • ADDRB7=8
  • ADDRB8=8
  • ADDRB9=8
  • CLKB=8
  • DIB=8
  • DOB=8
  • DOB0=8
  • DOB1=8
  • DOB2=8
  • DOB3=8
  • DOB4=8
  • DOB5=8
  • DOB6=8
  • DOB7=8
  • DOPB0=8
  • ENB=8
  • SSRB=8
  • WEB=8
SLICEL
  • BX=308
  • BY=193
  • CE=270
  • CIN=74
  • CLK=389
  • COUT=75
  • F1=840
  • F2=759
  • F3=707
  • F4=434
  • F5=54
  • FX=17
  • FXINA=27
  • FXINB=27
  • G1=822
  • G2=745
  • G3=673
  • G4=361
  • SR=271
  • X=626
  • XB=1
  • XQ=321
  • Y=535
  • YQ=292
SLICEL_C1VDD
  • 1=24
SLICEL_C2VDD
  • 1=18
SLICEL_CYMUXF
  • 0=83
  • 1=83
  • OUT=83
  • S0=83
SLICEL_CYMUXG
  • 0=75
  • 1=75
  • OUT=75
  • S0=75
SLICEL_F
  • A1=840
  • A2=759
  • A3=707
  • A4=434
  • D=841
SLICEL_F5MUX
  • F=160
  • G=160
  • OUT=160
  • S0=160
SLICEL_F6MUX
  • 0=27
  • 1=27
  • OUT=27
  • S0=27
SLICEL_FFX
  • CE=227
  • CK=321
  • D=321
  • Q=321
  • REV=20
  • SR=218
SLICEL_FFY
  • CE=207
  • CK=292
  • D=292
  • Q=292
  • REV=1
  • SR=199
SLICEL_G
  • A1=822
  • A2=745
  • A3=673
  • A4=361
  • D=826
SLICEL_GNDF
  • 0=55
SLICEL_GNDG
  • 0=53
SLICEL_XORF
  • 0=83
  • 1=83
  • O=83
SLICEL_XORG
  • 0=80
  • 1=80
  • O=80
SLICEM
  • BX=79
  • BY=385
  • CE=25
  • CLK=367
  • F1=380
  • F2=380
  • F3=380
  • F4=346
  • F5=34
  • FX=17
  • FXINA=34
  • FXINB=34
  • G1=385
  • G2=385
  • G3=385
  • G4=351
  • SR=351
  • X=346
  • XQ=1
  • Y=32
  • YQ=27
SLICEM_F
  • A1=380
  • A2=380
  • A3=380
  • A4=346
  • D=380
  • DI=346
  • WF1=334
  • WF2=334
  • WF3=334
  • WF4=334
  • WS=346
SLICEM_F5MUX
  • F=66
  • G=66
  • OUT=66
  • S0=66
SLICEM_F6MUX
  • 0=34
  • 1=34
  • OUT=34
  • S0=34
SLICEM_FFX
  • CE=1
  • CK=1
  • D=1
  • Q=1
SLICEM_FFY
  • CE=25
  • CK=27
  • D=27
  • Q=27
SLICEM_G
  • A1=385
  • A2=385
  • A3=385
  • A4=351
  • D=99
  • DI=351
  • WG1=334
  • WG2=334
  • WG3=334
  • WG4=334
  • WS=351
SLICEM_WSGEN
  • CK=351
  • WE=351
  • WE0=32
  • WSF=346
  • WSG=351
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-tq144-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s250e-tq144-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-tq144-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s250e-tq144-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-tq144-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s250e-tq144-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 129 129 0 0 0 0 0
bitgen 29 29 0 0 0 0 0
cse_server 2 2 0 0 0 0 0
elfcheck 75 75 0 0 0 0 0
libgen 9 5 0 0 0 0 0
map 42 32 0 0 0 0 0
ngc2edif 1 1 0 0 0 0 0
ngcbuild 35 35 0 0 0 0 0
ngdbuild 47 47 0 0 0 0 0
par 32 32 0 0 0 0 0
platgen 17 13 0 0 0 0 0
psf2Edward 5 5 0 0 0 0 0
trce 32 32 0 0 0 0 0
xdsgen 5 5 0 0 0 0 0
xps 18 17 0 0 0 0 0
xst 212 204 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/pp_db_xilinx_specific_options.htm ( 1 )
 
Project Statistics
PROPEXT_xilxSynthMaxFanout_virtex2=100000 PROP_Enable_Message_Filtering=false
PROP_FitterReportFormat=HTML PROP_LastAppliedGoal=Balanced
PROP_LastAppliedStrategy=Xilinx Default (unlocked) PROP_ManualCompileOrderImp=false
PROP_PropSpecInProjFile=Store all values PROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthTopFile=changed PROP_Top_Level_Module_Type=HDL
PROP_UseSmartGuide=false PROP_UserConstraintEditorPreference=Text Editor
PROP_intProjectCreationTimestamp=2013-01-15T10:51:21 PROP_intWbtProjectID=314A0CF2C5504D1492F1C1F4C1B6F4E4
PROP_intWbtProjectIteration=3 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_xilxBitgStart_IntDone=true
PROP_xst_otherCmdLineOptions=-use_new_parser yes PROP_AutoTop=false
PROP_DevFamily=Spartan3E PROP_DevDevice=xc3s250e
PROP_DevFamilyPMName=spartan3e PROP_DevPackage=tq144
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-4
PROP_PreferredLanguage=Verilog FILE_UCF=1
FILE_VERILOG=24
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FD=81 NGDBUILD_NUM_FDC=17 NGDBUILD_NUM_FDCE=3
NGDBUILD_NUM_FDE=143 NGDBUILD_NUM_FDPE=1 NGDBUILD_NUM_FDR=73 NGDBUILD_NUM_FDRE=254
NGDBUILD_NUM_FDRS=10 NGDBUILD_NUM_FDRSE=11 NGDBUILD_NUM_FDSE=48 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=19 NGDBUILD_NUM_INV=84 NGDBUILD_NUM_IOBUF=22 NGDBUILD_NUM_LUT1=110
NGDBUILD_NUM_LUT2=115 NGDBUILD_NUM_LUT2_D=4 NGDBUILD_NUM_LUT2_L=8 NGDBUILD_NUM_LUT3=567
NGDBUILD_NUM_LUT3_D=34 NGDBUILD_NUM_LUT3_L=56 NGDBUILD_NUM_LUT4=665 NGDBUILD_NUM_LUT4_D=65
NGDBUILD_NUM_LUT4_L=60 NGDBUILD_NUM_MUXCY=158 NGDBUILD_NUM_MUXF5=194 NGDBUILD_NUM_MUXF6=44
NGDBUILD_NUM_MUXF7=17 NGDBUILD_NUM_OBUF=26 NGDBUILD_NUM_RAM16X1D=302 NGDBUILD_NUM_RAM32X1S=32
NGDBUILD_NUM_RAMB16_S1=1 NGDBUILD_NUM_RAMB16_S9=1 NGDBUILD_NUM_RAMB16_S9_S9=8 NGDBUILD_NUM_SRL16=2
NGDBUILD_NUM_SRLC16E=27 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=163
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BSCAN_SPARTAN3=1 NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FD=81 NGDBUILD_NUM_FDC=17
NGDBUILD_NUM_FDCE=3 NGDBUILD_NUM_FDE=143 NGDBUILD_NUM_FDPE=1 NGDBUILD_NUM_FDR=73
NGDBUILD_NUM_FDRE=254 NGDBUILD_NUM_FDRS=10 NGDBUILD_NUM_FDRSE=11 NGDBUILD_NUM_FDSE=48
NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=41 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=84
NGDBUILD_NUM_LUT1=110 NGDBUILD_NUM_LUT2=115 NGDBUILD_NUM_LUT2_D=4 NGDBUILD_NUM_LUT2_L=8
NGDBUILD_NUM_LUT3=567 NGDBUILD_NUM_LUT3_D=34 NGDBUILD_NUM_LUT3_L=56 NGDBUILD_NUM_LUT4=665
NGDBUILD_NUM_LUT4_D=65 NGDBUILD_NUM_LUT4_L=60 NGDBUILD_NUM_MUXCY=158 NGDBUILD_NUM_MUXF5=194
NGDBUILD_NUM_MUXF6=44 NGDBUILD_NUM_MUXF7=17 NGDBUILD_NUM_OBUF=26 NGDBUILD_NUM_OBUFT=22
NGDBUILD_NUM_PULLDOWN=27 NGDBUILD_NUM_RAM32X1S=32 NGDBUILD_NUM_RAMB16_S1=1 NGDBUILD_NUM_RAMB16_S9=1
NGDBUILD_NUM_RAMB16_S9_S9=8 NGDBUILD_NUM_SRLC16E=29 NGDBUILD_NUM_TS_TIMESPEC=1 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=163
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s250e-4-tq144 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=100000 -bufg=24
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5