Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

software_version_and_target_device
betaFALSE build_version3247384
date_generatedFri Oct 15 16:23:50 2021 os_platformWIN64
product_versionVivado v2021.1 (64-bit) project_id161062e6b6164ef99308f0b9291b2f4e
project_iteration1 random_id4deba57076835d06bd8deaf4ecdfc228
registration_id4deba57076835d06bd8deaf4ecdfc228 route_designTRUE
target_devicexc7k70t target_familykintex7
target_packagefbg676 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i5-10210U CPU @ 1.60GHz cpu_speed2112 MHz
os_nameWindows Server 2016 or Windows 10 os_releasemajor release (build 9200)
system_ram16.000 GB total_processors1

vivado_usage
gui_handlers
applyrsbmultiautomationdialog_checkbox_tree=4 basedialog_apply=1 basedialog_cancel=9 basedialog_ok=42
basedialog_yes=4 cmdmsgdialog_ok=2 coretreetablepanel_core_tree_table=5 createconstraintsfilepanel_file_name=1
createnewdiagramdialog_design_name=1 creatersbportdialog_create_vector=1 creatersbportdialog_from=1 creatersbportdialog_port_name=2
exportplatformwizard_fixed_post_impl=1 filesetpanel_file_set_panel_tree=44 flownavigatortreepanel_flow_navigator_tree=19 fpgachooser_family=1
fpgachooser_fpga_table=1 fpgachooser_package=1 fpgachooser_speed=1 gettingstartedview_create_new_project=1
gettingstartedview_open_project=1 languagetemplatesdialog_templates_tree=4 logpanel_log_navigator=2 mainmenumgr_checkpoint=1
mainmenumgr_edit=4 mainmenumgr_export=3 mainmenumgr_file=10 mainmenumgr_flow=3
mainmenumgr_help=2 mainmenumgr_ip=3 mainmenumgr_project=6 mainmenumgr_reports=6
mainmenumgr_text_editor=2 mainmenumgr_tools=12 mainmenumgr_view=4 mainmenumgr_window=14
mainwinmenumgr_layout=6 newprojectwizard_do_not_specify_sources_at_this_time=2 newprojectwizard_project_is_a_vitis_platform=4 pacommandnames_auto_connect_ports=7
pacommandnames_auto_connect_target=1 pacommandnames_close_project=1 pacommandnames_create_top_hdl=2 pacommandnames_export_hardware=1
pacommandnames_goto_netlist_design=2 pacommandnames_language_templates=1 pacommandnames_package_pins_window=1 pacommandnames_ports_window=1
pacommandnames_regenerate_layout=5 pacommandnames_save_design=2 pacommandnames_save_rsb_design=5 pacommandnames_validate_rsb_design=1
paviews_code=6 paviews_project_summary=6 planaheadtab_refresh_changed_modules=1 programdebugtab_open_recently_opened_target=1
programdebugtab_open_target=1 programdebugtab_program_device=1 programfpgadialog_program=1 projectnamechooser_create_project_subdirectory=2
projectnamechooser_project_name=1 projecttab_close_design=1 rdicommands_custom_commands=7 rdicommands_delete=1
rdicommands_save_file=18 rdicommands_settings=4 rdicommands_undo=1 rsbaddmoduledialog_module_list=1
rsbapplyautomationbar_run_block_automation=1 rsbapplyautomationbar_run_connection_automation=2 rsbblockproppanels_name=2 rsbexternalinterfaceproppanels_name=5
rsbexternalportproppanels_name=2 saveprojectutils_save=2 selectmenu_highlight=6 settingsdialog_options_tree=7
signaltreepanel_signal_tree_table=99 srcchooserpanel_add_hdl_and_netlist_files_to_your_project=2 syntheticagettingstartedview_recent_projects=2 systembuildermenu_add_module=2
systembuildermenu_create_port=1 systembuilderview_add_ip=3 systembuilderview_expand_collapse=2 systembuilderview_pinning=12
systemtreeview_system_tree=1 taskbanner_close=1 touchpointsurveydialog_no=2
java_command_handlers
addsources=2 autoconnectport=7 autoconnecttarget=1 closeproject=1
createblockdesign=1 createtophdl=2 customizersbblock=10 editdelete=2
editundo=1 exitapp=2 launchprogramfpga=1 launchvitis=1
newexporthardware=1 newproject=1 openblockdesign=4 openhardwaremanager=1
openproject=1 regeneratersblayout=5 runbitgen=4 runsynthesis=5
savedesign=2 saversbdesign=5 showview=2 toolssettings=4
toolstemplates=1 validatersbdesign=1 viewtasksynthesis=2
other_data
guimode=4
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=0 export_simulation_ies=0
export_simulation_modelsim=0 export_simulation_questa=0 export_simulation_riviera=0 export_simulation_vcs=0
export_simulation_xsim=0 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=5 synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog target_simulator=XSim totalimplruns=17 totalsynthesisruns=17

unisim_transformation
post_unisim_transformation
and2b1l=1 bscane2=1 bufg=3 carry4=117
dsp48e1=4 fdce=38 fdpe=6 fdre=2391
fdse=138 gnd=403 ibuf=15 lut1=73
lut2=285 lut3=529 lut4=573 lut5=564
lut6=1052 mmcme2_adv=1 muxf7=110 obuf=37
ramb36e1=16 ramd32=160 rams32=32 srl16e=117
srlc16e=8 srlc32e=1 vcc=263
pre_unisim_transformation
and2b1l=1 bscane2=1 bufg=3 carry4=117
dsp48e1=4 fdce=38 fdpe=6 fdre=2391
fdse=138 gnd=403 ibuf=15 lut1=73
lut2=285 lut3=529 lut4=573 lut5=484
lut6=972 lut6_2=80 mmcme2_adv=1 muxf7=110
obuf=37 ram32m=16 ram32x1d=32 ramb36e1=16
srl16e=117 srlc16e=8 srlc32e=1 vcc=263

phys_opt_design_post_place
command_line_options
-aggressive_hold_fix=default::[not_specified] -bram_register_opt=default::[not_specified] -clock_opt=default::[not_specified] -critical_cell_opt=default::[not_specified]
-critical_pin_opt=default::[not_specified] -directive=default::[not_specified] -dsp_register_opt=default::[not_specified] -effort_level=default::[not_specified]
-fanout_opt=default::[not_specified] -hold_fix=default::[not_specified] -insert_negative_edge_ffs=default::[not_specified] -multi_clock_opt=default::[not_specified]
-placement_opt=default::[not_specified] -restruct_opt=default::[not_specified] -retime=default::[not_specified] -rewire=default::[not_specified]
-shift_register_opt=default::[not_specified] -uram_register_opt=default::[not_specified] -verbose=default::[not_specified] -vhfn=default::[not_specified]

power_opt_design
command_line_options_spo
-cell_types=default::all -clocks=default::[not_specified] -exclude_cells=default::[not_specified] -include_cells=default::[not_specified]
usage
bram_ports_augmented=0 bram_ports_newly_gated=0 bram_ports_total=32 flow_state=default
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=2559 srls_augmented=0
srls_newly_gated=0 srls_total=120

ip_statistics
IP_Integrator/1
bdsource=USER core_container=NA da_axi4_cnt=5 da_mb_cnt=1
iptotal=1 maxhierdepth=1 numblks=26 numhdlrefblks=1
numhierblks=9 numhlsblks=0 numnonxlnxblks=0 numpkgbdblks=0
numreposblks=17 numsysgenblks=0 synth_mode=OOC_per_IP x_iplanguage=VERILOG
x_iplibrary=BlockDiagram x_ipname=cpu_system x_ipvendor=xilinx.com x_ipversion=1.00.a
MDM/1
x_ipversion=1.00.a c_addr_size=32 c_avoid_primitives=0 c_bscanid=76547328
c_data_size=32 c_dbg_mem_access=0 c_dbg_reg_access=0 c_debug_interface=0
c_ext_trig_reset_value=0xF1234 c_family=kintex7 c_interconnect=2 c_jtag_chain=2
c_lmb_protocol=0 c_m_axi_addr_width=32 c_m_axi_data_width=32 c_m_axi_thread_id_width=1
c_m_axis_data_width=32 c_m_axis_id_width=7 c_mb_dbg_ports=1 c_s_axi_aclk_freq_hz=100000000
c_s_axi_addr_width=4 c_s_axi_data_width=32 c_trace_async_reset=0 c_trace_clk_freq_hz=200000000
c_trace_clk_out_phase=90 c_trace_data_width=32 c_trace_id=110 c_trace_output=0
c_trace_protocol=1 c_use_bscan=0 c_use_config_reset=0 c_use_cross_trigger=0
c_use_uart=0 core_container=NA iptotal=1 x_ipcorerevision=21
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=mdm x_ipproduct=Vivado 2021.1
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=3.2
MicroBlaze/1
c_addr_tag_bits=17 c_allow_dcache_wr=1 c_allow_icache_wr=1 c_area_optimized=0
c_async_interrupt=1 c_async_wakeup=3 c_avoid_primitives=0 c_base_vectors=0x0000000000000000
c_branch_target_cache_size=0 c_cache_byte_size=8192 c_d_axi=1 c_d_lmb=1
c_d_lmb_protocol=0 c_daddr_size=32 c_data_size=32 c_dcache_addr_tag=17
c_dcache_always_used=1 c_dcache_baseaddr=0x0000000000000000 c_dcache_byte_size=8192 c_dcache_data_width=0
c_dcache_force_tag_lutram=0 c_dcache_highaddr=0x000000003FFFFFFF c_dcache_line_len=4 c_dcache_use_writeback=0
c_dcache_victims=0 c_debug_counter_width=32 c_debug_enabled=1 c_debug_event_counters=5
c_debug_external_trace=0 c_debug_interface=0 c_debug_latency_counters=1 c_debug_profile_size=0
c_debug_trace_async_reset=0 c_debug_trace_size=8192 c_div_zero_exception=0 c_dynamic_bus_sizing=0
c_ecc_use_ce_exception=0 c_edge_is_positive=1 c_endianness=1 c_family=kintex7
c_fault_tolerant=0 c_fpu_exception=0 c_freq=100000000 c_fsl_exception=0
c_fsl_links=0 c_i_axi=0 c_i_lmb=1 c_i_lmb_protocol=0
c_iaddr_size=32 c_icache_always_used=1 c_icache_baseaddr=0x0000000000000000 c_icache_data_width=0
c_icache_force_tag_lutram=0 c_icache_highaddr=0x000000003FFFFFFF c_icache_line_len=4 c_icache_streams=0
c_icache_victims=0 c_ill_opcode_exception=0 c_imprecise_exceptions=0 c_instance=cpu_system_microblaze_0_0
c_instr_size=32 c_interconnect=2 c_interrupt_is_edge=0 c_lmb_data_size=32
c_lockstep_master=0 c_lockstep_slave=0 c_m0_axis_data_width=32 c_m10_axis_data_width=32
c_m11_axis_data_width=32 c_m12_axis_data_width=32 c_m13_axis_data_width=32 c_m14_axis_data_width=32
c_m15_axis_data_width=32 c_m1_axis_data_width=32 c_m2_axis_data_width=32 c_m3_axis_data_width=32
c_m4_axis_data_width=32 c_m5_axis_data_width=32 c_m6_axis_data_width=32 c_m7_axis_data_width=32
c_m8_axis_data_width=32 c_m9_axis_data_width=32 c_m_axi_d_bus_exception=0 c_m_axi_dc_addr_width=32
c_m_axi_dc_aruser_width=5 c_m_axi_dc_awuser_width=5 c_m_axi_dc_buser_width=1 c_m_axi_dc_data_width=32
c_m_axi_dc_exclusive_access=0 c_m_axi_dc_ruser_width=1 c_m_axi_dc_thread_id_width=1 c_m_axi_dc_user_value=31
c_m_axi_dc_wuser_width=1 c_m_axi_dp_addr_width=32 c_m_axi_dp_data_width=32 c_m_axi_dp_exclusive_access=0
c_m_axi_dp_thread_id_width=1 c_m_axi_i_bus_exception=0 c_m_axi_ic_addr_width=32 c_m_axi_ic_aruser_width=5
c_m_axi_ic_awuser_width=5 c_m_axi_ic_buser_width=1 c_m_axi_ic_data_width=32 c_m_axi_ic_ruser_width=1
c_m_axi_ic_thread_id_width=1 c_m_axi_ic_user_value=31 c_m_axi_ic_wuser_width=1 c_m_axi_ip_addr_width=32
c_m_axi_ip_data_width=32 c_m_axi_ip_thread_id_width=1 c_mmu_dtlb_size=4 c_mmu_itlb_size=2
c_mmu_privileged_instr=0 c_mmu_tlb_access=3 c_mmu_zones=16 c_num_sync_ff_clk=2
c_num_sync_ff_clk_debug=2 c_num_sync_ff_clk_irq=1 c_num_sync_ff_dbg_clk=1 c_num_sync_ff_dbg_trace_clk=2
c_number_of_pc_brk=1 c_number_of_rd_addr_brk=0 c_number_of_wr_addr_brk=0 c_opcode_0x0_illegal=0
c_optimization=0 c_pc_width=32 c_piaddr_size=32 c_pvr=0
c_pvr_user1=0x00 c_pvr_user2=0x00000000 c_reset_msr=0x00000000 c_s0_axis_data_width=32
c_s10_axis_data_width=32 c_s11_axis_data_width=32 c_s12_axis_data_width=32 c_s13_axis_data_width=32
c_s14_axis_data_width=32 c_s15_axis_data_width=32 c_s1_axis_data_width=32 c_s2_axis_data_width=32
c_s3_axis_data_width=32 c_s4_axis_data_width=32 c_s5_axis_data_width=32 c_s6_axis_data_width=32
c_s7_axis_data_width=32 c_s8_axis_data_width=32 c_s9_axis_data_width=32 c_sco=0
c_unaligned_exceptions=0 c_use_barrel=1 c_use_branch_target_cache=0 c_use_config_reset=0
c_use_dcache=0 c_use_div=1 c_use_ext_brk=0 c_use_ext_nm_brk=0
c_use_extended_fsl_instr=0 c_use_fpu=0 c_use_hw_mul=2 c_use_icache=0
c_use_interrupt=2 c_use_mmu=0 c_use_msr_instr=1 c_use_non_secure=0
c_use_pcmp_instr=1 c_use_reorder_instr=1 c_use_stack_protection=0 core_container=NA
g_template_list=0 iptotal=1 x_ipcorerevision=6 x_iplanguage=VERILOG
x_iplibrary=ip x_ipname=microblaze x_ipproduct=Vivado 2021.1 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=11.0
axi_crossbar_v2_1_25_axi_crossbar/1
c_axi_addr_width=32 c_axi_aruser_width=1 c_axi_awuser_width=1 c_axi_buser_width=1
c_axi_data_width=32 c_axi_id_width=1 c_axi_protocol=2 c_axi_ruser_width=1
c_axi_supports_user_signals=0 c_axi_wuser_width=1 c_connectivity_mode=0 c_family=kintex7
c_m_axi_addr_width=0x000000100000001000000010000000100000001000000010 c_m_axi_base_addr=0x000000004500000000000000410000000000000040000000000000004200000000000000430000000000000044000000 c_m_axi_read_connectivity=0x000000010000000100000001000000010000000100000001 c_m_axi_read_issuing=0x000000010000000100000001000000010000000100000001
c_m_axi_secure=0x000000000000000000000000000000000000000000000000 c_m_axi_write_connectivity=0x000000010000000100000001000000010000000100000001 c_m_axi_write_issuing=0x000000010000000100000001000000010000000100000001 c_num_addr_ranges=1
c_num_master_slots=6 c_num_slave_slots=1 c_r_register=1 c_s_axi_arb_priority=0x00000000
c_s_axi_base_id=0x00000000 c_s_axi_read_acceptance=0x00000001 c_s_axi_single_thread=0x00000001 c_s_axi_thread_id_width=0x00000000
c_s_axi_write_acceptance=0x00000001 core_container=NA iptotal=1 x_ipcorerevision=25
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=axi_crossbar x_ipproduct=Vivado 2021.1
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=2.1
axi_gpio/1
c_all_inputs=0 c_all_inputs_2=0 c_all_outputs=1 c_all_outputs_2=1
c_dout_default=0x00000000 c_dout_default_2=0x00000000 c_family=kintex7 c_gpio2_width=12
c_gpio_width=24 c_interrupt_present=0 c_is_dual=1 c_s_axi_addr_width=9
c_s_axi_data_width=32 c_tri_default=0xFFFFFFFF c_tri_default_2=0xFFFFFFFF core_container=NA
iptotal=1 x_ipcorerevision=26 x_iplanguage=VERILOG x_iplibrary=ip
x_ipname=axi_gpio x_ipproduct=Vivado 2021.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=2.0
axi_gpio/2
c_all_inputs=1 c_all_inputs_2=1 c_all_outputs=0 c_all_outputs_2=0
c_dout_default=0x00000000 c_dout_default_2=0x00000000 c_family=kintex7 c_gpio2_width=4
c_gpio_width=8 c_interrupt_present=1 c_is_dual=1 c_s_axi_addr_width=9
c_s_axi_data_width=32 c_tri_default=0xFFFFFFFF c_tri_default_2=0xFFFFFFFF core_container=NA
iptotal=1 x_ipcorerevision=26 x_iplanguage=VERILOG x_iplibrary=ip
x_ipname=axi_gpio x_ipproduct=Vivado 2021.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=2.0
axi_intc/1
c_addr_width=32 c_async_intr=0xFFFFFFF0 c_cascade_master=0 c_disable_synchronizers=1
c_en_cascade_mode=0 c_enable_async=0 c_family=kintex7 c_has_cie=1
c_has_fast=1 c_has_ilr=0 c_has_ipr=1 c_has_ivr=1
c_has_sie=1 c_instance=cpu_system_microblaze_0_axi_intc_0 c_irq_active=0x1 c_irq_is_level=1
c_ivar_reset_value=0x0000000000000010 c_kind_of_edge=0xFFFFFFFF c_kind_of_intr=0xfffffff2 c_kind_of_lvl=0xFFFFFFFF
c_mb_clk_not_connected=1 c_num_intr_inputs=4 c_num_sw_intr=0 c_num_sync_ff=2
c_s_axi_addr_width=9 c_s_axi_data_width=32 core_container=NA iptotal=1
x_ipcorerevision=15 x_iplanguage=VERILOG x_iplibrary=ip x_ipname=axi_intc
x_ipproduct=Vivado 2021.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=4.1
axi_timer/1
c_count_width=32 c_family=kintex7 c_gen0_assert=1 c_gen1_assert=1
c_one_timer_only=0 c_s_axi_addr_width=5 c_s_axi_data_width=32 c_trig0_assert=1
c_trig1_assert=1 core_container=NA iptotal=1 x_ipcorerevision=26
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=axi_timer x_ipproduct=Vivado 2021.1
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=2.0
axi_uartlite/1
c_baudrate=115200 c_data_bits=8 c_family=kintex7 c_odd_parity=0
c_s_axi_aclk_freq_hz=100000000 c_s_axi_addr_width=4 c_s_axi_data_width=32 c_use_parity=0
core_container=NA iptotal=1 x_ipcorerevision=28 x_iplanguage=VERILOG
x_iplibrary=ip x_ipname=axi_uartlite x_ipproduct=Vivado 2021.1 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=2.0
blk_mem_gen_v8_4_4/1
c_addra_width=32 c_addrb_width=32 c_algorithm=1 c_axi_id_width=4
c_axi_slave_type=0 c_axi_type=1 c_byte_size=8 c_common_clk=0
c_count_18k_bram=0 c_count_36k_bram=16 c_ctrl_ecc_algo=NONE c_default_data=0
c_disable_warn_bhv_coll=0 c_disable_warn_bhv_range=0 c_elaboration_dir=./ c_en_deepsleep_pin=0
c_en_ecc_pipe=0 c_en_rdaddra_chg=0 c_en_rdaddrb_chg=0 c_en_safety_ckt=1
c_en_shutdown_pin=0 c_en_sleep_pin=0 c_enable_32bit_address=1 c_est_power_summary=Estimated Power for IP _ 20.388 mW
c_family=kintex7 c_has_axi_id=0 c_has_ena=1 c_has_enb=1
c_has_injecterr=0 c_has_mem_output_regs_a=0 c_has_mem_output_regs_b=0 c_has_mux_output_regs_a=0
c_has_mux_output_regs_b=0 c_has_regcea=0 c_has_regceb=0 c_has_rsta=1
c_has_rstb=1 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0 c_init_file=cpu_system_lmb_bram_0.mem
c_init_file_name=no_coe_file_loaded c_inita_val=0 c_initb_val=0 c_interface_type=0
c_load_init_file=0 c_mem_type=2 c_mux_pipeline_stages=0 c_prim_type=1
c_read_depth_a=16384 c_read_depth_b=16384 c_read_latency_a=1 c_read_latency_b=1
c_read_width_a=32 c_read_width_b=32 c_rst_priority_a=CE c_rst_priority_b=CE
c_rstram_a=0 c_rstram_b=0 c_sim_collision_check=ALL c_use_bram_block=1
c_use_byte_wea=1 c_use_byte_web=1 c_use_default_data=0 c_use_ecc=0
c_use_softecc=0 c_use_uram=0 c_wea_width=4 c_web_width=4
c_write_depth_a=16384 c_write_depth_b=16384 c_write_mode_a=WRITE_FIRST c_write_mode_b=WRITE_FIRST
c_write_width_a=32 c_write_width_b=32 c_xdevicefamily=kintex7 core_container=false
iptotal=1 x_ipcorerevision=4 x_iplanguage=VERILOG x_iplibrary=ip
x_ipname=blk_mem_gen x_ipproduct=Vivado 2021.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=8.4
clk_wiz_v6_0_8_0_0/1
clkin1_period=10.000 clkin2_period=10.000 clock_mgr_type=NA component_name=cpu_system_clk_wiz_1_0
core_container=NA enable_axi=0 feedback_source=FDBK_AUTO feedback_type=SINGLE
iptotal=1 manual_override=false num_out_clk=1 primitive=MMCM
use_dyn_phase_shift=false use_dyn_reconfig=false use_inclk_stopped=false use_inclk_switchover=false
use_locked=true use_max_i_jitter=false use_min_o_jitter=false use_phase_alignment=true
use_power_down=false use_reset=true
lmb_bram_if_cntlr/1
c_baseaddr=0x0000000000000000 c_bram_awidth=32 c_ce_counter_width=0 c_ce_failing_registers=0
c_ecc=0 c_ecc_onoff_register=0 c_ecc_onoff_reset_value=1 c_ecc_status_registers=0
c_family=kintex7 c_fault_inject=0 c_highaddr=0x000000000000FFFF c_interconnect=0
c_lmb_awidth=32 c_lmb_dwidth=32 c_lmb_protocol=0 c_mask=0x0000000040000000
c_mask1=0x0000000000800000 c_mask2=0x0000000000800000 c_mask3=0x0000000000800000 c_num_lmb=1
c_s_axi_ctrl_addr_width=32 c_s_axi_ctrl_data_width=32 c_ue_failing_registers=0 c_write_access=2
core_container=NA iptotal=1 x_ipcorerevision=19 x_iplanguage=VERILOG
x_iplibrary=ip x_ipname=lmb_bram_if_cntlr x_ipproduct=Vivado 2021.1 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=4.0
lmb_bram_if_cntlr/2
c_baseaddr=0x0000000000000000 c_bram_awidth=32 c_ce_counter_width=0 c_ce_failing_registers=0
c_ecc=0 c_ecc_onoff_register=0 c_ecc_onoff_reset_value=1 c_ecc_status_registers=0
c_family=kintex7 c_fault_inject=0 c_highaddr=0x000000000000FFFF c_interconnect=0
c_lmb_awidth=32 c_lmb_dwidth=32 c_lmb_protocol=0 c_mask=0x0000000000000000
c_mask1=0x0000000000800000 c_mask2=0x0000000000800000 c_mask3=0x0000000000800000 c_num_lmb=1
c_s_axi_ctrl_addr_width=32 c_s_axi_ctrl_data_width=32 c_ue_failing_registers=0 c_write_access=2
core_container=NA iptotal=1 x_ipcorerevision=19 x_iplanguage=VERILOG
x_iplibrary=ip x_ipname=lmb_bram_if_cntlr x_ipproduct=Vivado 2021.1 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=4.0
lmb_v10/1
c_ext_reset_high=1 c_lmb_awidth=32 c_lmb_dwidth=32 c_lmb_num_slaves=1
c_lmb_protocol=0 core_container=NA iptotal=2 x_ipcorerevision=11
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=lmb_v10 x_ipproduct=Vivado 2021.1
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=3.0
lvl_indicator/1
c_s_axi_addr_width=4 c_s_axi_data_width=32 core_container=NA iptotal=1
x_ipcorerevision=1 x_iplanguage=VERILOG x_iplibrary=module_ref x_ipname=lvl_indicator
x_ipproduct=Vivado 2021.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=1.0
proc_sys_reset/1
c_aux_reset_high=0 c_aux_rst_width=4 c_ext_reset_high=1 c_ext_rst_width=4
c_family=kintex7 c_num_bus_rst=1 c_num_interconnect_aresetn=1 c_num_perp_aresetn=1
c_num_perp_rst=1 core_container=NA iptotal=1 x_ipcorerevision=13
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=proc_sys_reset x_ipproduct=Vivado 2021.1
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=5.0
xlconcat_v2_1_4_xlconcat/1
core_container=NA dout_width=4 in0_width=1 in100_width=1
in101_width=1 in102_width=1 in103_width=1 in104_width=1
in105_width=1 in106_width=1 in107_width=1 in108_width=1
in109_width=1 in10_width=1 in110_width=1 in111_width=1
in112_width=1 in113_width=1 in114_width=1 in115_width=1
in116_width=1 in117_width=1 in118_width=1 in119_width=1
in11_width=1 in120_width=1 in121_width=1 in122_width=1
in123_width=1 in124_width=1 in125_width=1 in126_width=1
in127_width=1 in12_width=1 in13_width=1 in14_width=1
in15_width=1 in16_width=1 in17_width=1 in18_width=1
in19_width=1 in1_width=1 in20_width=1 in21_width=1
in22_width=1 in23_width=1 in24_width=1 in25_width=1
in26_width=1 in27_width=1 in28_width=1 in29_width=1
in2_width=1 in30_width=1 in31_width=1 in32_width=1
in33_width=1 in34_width=1 in35_width=1 in36_width=1
in37_width=1 in38_width=1 in39_width=1 in3_width=1
in40_width=1 in41_width=1 in42_width=1 in43_width=1
in44_width=1 in45_width=1 in46_width=1 in47_width=1
in48_width=1 in49_width=1 in4_width=1 in50_width=1
in51_width=1 in52_width=1 in53_width=1 in54_width=1
in55_width=1 in56_width=1 in57_width=1 in58_width=1
in59_width=1 in5_width=1 in60_width=1 in61_width=1
in62_width=1 in63_width=1 in64_width=1 in65_width=1
in66_width=1 in67_width=1 in68_width=1 in69_width=1
in6_width=1 in70_width=1 in71_width=1 in72_width=1
in73_width=1 in74_width=1 in75_width=1 in76_width=1
in77_width=1 in78_width=1 in79_width=1 in7_width=1
in80_width=1 in81_width=1 in82_width=1 in83_width=1
in84_width=1 in85_width=1 in86_width=1 in87_width=1
in88_width=1 in89_width=1 in8_width=1 in90_width=1
in91_width=1 in92_width=1 in93_width=1 in94_width=1
in95_width=1 in96_width=1 in97_width=1 in98_width=1
in99_width=1 in9_width=1 iptotal=1 num_ports=4
x_ipcorerevision=4 x_iplanguage=VERILOG x_iplibrary=ip x_ipname=xlconcat
x_ipproduct=Vivado 2021.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=2.1

report_design_analysis
command_line_options
-append=default::[not_specified] -bounding_boxes=default::[not_specified] -cells=default::[not_specified] -complexity=default::[not_specified]
-congestion=default::[not_specified] -end_point_clocks=default::[not_specified] -extend=default::[not_specified] -extract_metrics=default::[not_specified]
-file=default::[not_specified] -full_logical_pin=default::[not_specified] -hierarchical_depth=default::[not_specified] -hold=default::[not_specified]
-logic_level_dist_paths=default::[not_specified] -logic_level_distribution=default::[not_specified] -logic_levels=default::[not_specified] -max_level=default::[not_specified]
-max_paths=default::[not_specified] -min_congestion_level=default::5 -min_level=default::[not_specified] -name=default::[not_specified]
-no_header=default::[not_specified] -of_timing_paths=default::[not_specified] -pploc_distance=default::[not_specified] -qor_summary=[specified]
-quiet=default::[not_specified] -return_string=default::[not_specified] -return_timing_paths=default::[not_specified] -routed_vs_estimated=default::[not_specified]
-routes=default::[not_specified] -setup=default::[not_specified] -show_all_congestion_windows=default::false -suggestion=default::[not_specified]
-timing=default::[not_specified] -verbose=default::[not_specified]
usage
runtime=0.517 secs
usage_count
qor_summary=4

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -max_msgs_per_check=default::[not_specified]
-messages=default::[not_specified] -name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified]
-ruledecks=default::[not_specified] -upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
cfgbvs-1=1 dpip-1=8 dpop-1=1 dpop-2=1

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -merge_exceptions =default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified]
-return_string=default::[not_specified] -slack_lesser_than=default::[not_specified] -waived=default::[not_specified]
results
lutar-1=1 timing-18=51 timing-9=1

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -hierarchical_depth=default::4 -l=default::[not_specified] -name=default::[not_specified]
-no_propagation=default::[not_specified] -return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified]
-vid=default::[not_specified] -xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers) board_selection=medium (10"x10") bram=0.007064 clocks=0.012077
confidence_level_clock_activity=High confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium
confidence_level_io_activity=Low confidence_level_overall=Low customer=TBD customer_class=TBD
devstatic=0.083917 die=xc7k70tfbg676-1 dsp=0.002170 dsp_output_toggle=12.500000
dynamic=0.138914 effective_thetaja=1.88 enable_probability=0.990000 family=kintex7
ff_toggle=12.500000 flow_state=routed heatsink=medium (Medium Profile) i/o=0.000380
input_toggle=12.500000 junction_temp=25.4 (C) logic=0.004936 mgtavcc_dynamic_current=0.000000
mgtavcc_static_current=0.000000 mgtavcc_total_current=0.000000 mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000
mgtavtt_static_current=0.000000 mgtavtt_total_current=0.000000 mgtavtt_voltage=1.200000 mgtvccaux_dynamic_current=0.000000
mgtvccaux_static_current=0.000000 mgtvccaux_total_current=0.000000 mgtvccaux_voltage=1.800000 mmcm=0.105861
netlist_net_matched=NA off-chip_power=0.000000 on-chip_power=0.222831 output_enable=1.000000
output_load=5.000000 output_toggle=12.500000 package=fbg676 pct_clock_constrained=5.000000
pct_inputs_defined=6 platform=nt64 process=typical ram_enable=50.000000
ram_write=50.000000 read_saif=False set/reset_probability=0.000000 signal_rate=False
signals=0.006425 simulation_file=None speedgrade=-1 static_prob=False
temp_grade=commercial thetajb=6.7 (C/W) thetasa=3.4 (C/W) toggle_rate=False
user_board_temp=25.0 (C) user_effective_thetaja=1.88 user_junc_temp=25.4 (C) user_thetajb=6.7 (C/W)
user_thetasa=3.4 (C/W) vccadc_dynamic_current=0.000000 vccadc_static_current=0.020000 vccadc_total_current=0.020000
vccadc_voltage=1.800000 vccaux_dynamic_current=0.058589 vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000
vccaux_io_total_current=0.000000 vccaux_io_voltage=1.800000 vccaux_static_current=0.011947 vccaux_total_current=0.070536
vccaux_voltage=1.800000 vccbram_dynamic_current=0.000607 vccbram_static_current=0.000886 vccbram_total_current=0.001494
vccbram_voltage=1.000000 vccint_dynamic_current=0.032600 vccint_static_current=0.022226 vccint_total_current=0.054826
vccint_voltage=1.000000 vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000 vcco12_total_current=0.000000
vcco12_voltage=1.200000 vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000 vcco135_total_current=0.000000
vcco135_voltage=1.350000 vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000 vcco15_total_current=0.000000
vcco15_voltage=1.500000 vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000 vcco18_total_current=0.000000
vcco18_voltage=1.800000 vcco25_dynamic_current=0.000000 vcco25_static_current=0.000000 vcco25_total_current=0.000000
vcco25_voltage=2.500000 vcco33_dynamic_current=0.000075 vcco33_static_current=0.001000 vcco33_total_current=0.001075
vcco33_voltage=3.300000 version=2021.1

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_prohibited=0 bufgctrl_used=4
bufgctrl_util_percentage=12.50 bufhce_available=96 bufhce_fixed=0 bufhce_prohibited=0
bufhce_used=0 bufhce_util_percentage=0.00 bufio_available=24 bufio_fixed=0
bufio_prohibited=0 bufio_used=0 bufio_util_percentage=0.00 bufmrce_available=12
bufmrce_fixed=0 bufmrce_prohibited=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=24 bufr_fixed=0 bufr_prohibited=0 bufr_used=0
bufr_util_percentage=0.00 mmcme2_adv_available=6 mmcme2_adv_fixed=0 mmcme2_adv_prohibited=0
mmcme2_adv_used=1 mmcme2_adv_util_percentage=16.67 plle2_adv_available=6 plle2_adv_fixed=0
plle2_adv_prohibited=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsp48e1_only_used=4 dsps_available=240 dsps_fixed=0 dsps_prohibited=0
dsps_used=4 dsps_util_percentage=1.67
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_i_dci=0
diff_hstl_i_dci_18=0 diff_hstl_ii=0 diff_hstl_ii_18=0 diff_hstl_ii_dci=0
diff_hstl_ii_dci_18=0 diff_hstl_ii_t_dci=0 diff_hstl_ii_t_dci_18=0 diff_hsul_12=0
diff_hsul_12_dci=0 diff_mobile_ddr=0 diff_sstl12=0 diff_sstl12_dci=0
diff_sstl12_t_dci=0 diff_sstl135=0 diff_sstl135_dci=0 diff_sstl135_r=0
diff_sstl135_t_dci=0 diff_sstl15=0 diff_sstl15_dci=0 diff_sstl15_r=0
diff_sstl15_t_dci=0 diff_sstl18_i=0 diff_sstl18_i_dci=0 diff_sstl18_ii=0
diff_sstl18_ii_dci=0 diff_sstl18_ii_t_dci=0 hslvdci_15=0 hslvdci_18=0
hstl_i=0 hstl_i_12=0 hstl_i_18=0 hstl_i_dci=0
hstl_i_dci_18=0 hstl_ii=0 hstl_ii_18=0 hstl_ii_dci=0
hstl_ii_dci_18=0 hstl_ii_t_dci=0 hstl_ii_t_dci_18=0 hsul_12=0
hsul_12_dci=0 lvcmos12=0 lvcmos15=0 lvcmos18=0
lvcmos25=0 lvcmos33=1 lvdci_15=0 lvdci_18=0
lvdci_dv2_15=0 lvdci_dv2_18=0 lvds=0 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl12=0 sstl12_dci=0
sstl12_t_dci=0 sstl135=0 sstl135_dci=0 sstl135_r=0
sstl135_t_dci=0 sstl15=0 sstl15_dci=0 sstl15_r=0
sstl15_t_dci=0 sstl18_i=0 sstl18_i_dci=0 sstl18_ii=0
sstl18_ii_dci=0 sstl18_ii_t_dci=0 tmds_33=0
memory
block_ram_tile_available=135 block_ram_tile_fixed=0 block_ram_tile_prohibited=0 block_ram_tile_used=16
block_ram_tile_util_percentage=11.85 ramb18_available=270 ramb18_fixed=0 ramb18_prohibited=0
ramb18_used=0 ramb18_util_percentage=0.00 ramb36_fifo_available=135 ramb36_fifo_fixed=0
ramb36_fifo_prohibited=0 ramb36_fifo_used=16 ramb36_fifo_util_percentage=11.85 ramb36e1_only_used=16
primitives
and2b1l_functional_category=Others and2b1l_used=1 bscane2_functional_category=Others bscane2_used=1
bufg_functional_category=Clock bufg_used=4 carry4_functional_category=CarryLogic carry4_used=117
dsp48e1_functional_category=Block Arithmetic dsp48e1_used=4 fdce_functional_category=Flop & Latch fdce_used=38
fdpe_functional_category=Flop & Latch fdpe_used=6 fdre_functional_category=Flop & Latch fdre_used=2379
fdse_functional_category=Flop & Latch fdse_used=136 ibuf_functional_category=IO ibuf_used=15
lut1_functional_category=LUT lut1_used=52 lut2_functional_category=LUT lut2_used=287
lut3_functional_category=LUT lut3_used=529 lut4_functional_category=LUT lut4_used=560
lut5_functional_category=LUT lut5_used=568 lut6_functional_category=LUT lut6_used=985
mmcme2_adv_functional_category=Clock mmcme2_adv_used=1 muxf7_functional_category=MuxFx muxf7_used=91
obuf_functional_category=IO obuf_used=37 ramb36e1_functional_category=Block Memory ramb36e1_used=16
ramd32_functional_category=Distributed Memory ramd32_used=160 rams32_functional_category=Distributed Memory rams32_used=32
srl16e_functional_category=Distributed Memory srl16e_used=112 srlc16e_functional_category=Distributed Memory srlc16e_used=7
srlc32e_functional_category=Distributed Memory srlc32e_used=1
slice_logic
f7_muxes_available=20500 f7_muxes_fixed=0 f7_muxes_prohibited=0 f7_muxes_used=91
f7_muxes_util_percentage=0.44 f8_muxes_available=10250 f8_muxes_fixed=0 f8_muxes_prohibited=0
f8_muxes_used=0 f8_muxes_util_percentage=0.00 lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=96
lut_as_logic_available=41000 lut_as_logic_fixed=0 lut_as_logic_prohibited=0 lut_as_logic_used=2468
lut_as_logic_util_percentage=6.02 lut_as_memory_available=13400 lut_as_memory_fixed=0 lut_as_memory_prohibited=0
lut_as_memory_used=172 lut_as_memory_util_percentage=1.28 lut_as_shift_register_fixed=0 lut_as_shift_register_used=76
register_as_and_or_available=82000 register_as_and_or_fixed=0 register_as_and_or_prohibited=0 register_as_and_or_used=1
register_as_and_or_util_percentage=<0.01 register_as_flip_flop_available=82000 register_as_flip_flop_fixed=0 register_as_flip_flop_prohibited=0
register_as_flip_flop_used=2559 register_as_flip_flop_util_percentage=3.12 register_as_latch_available=82000 register_as_latch_fixed=0
register_as_latch_prohibited=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00 slice_luts_available=41000
slice_luts_fixed=0 slice_luts_prohibited=0 slice_luts_used=2640 slice_luts_util_percentage=6.44
slice_registers_available=82000 slice_registers_fixed=0 slice_registers_prohibited=0 slice_registers_used=2560
slice_registers_util_percentage=3.12 lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=96 lut_as_logic_available=41000
lut_as_logic_fixed=0 lut_as_logic_prohibited=0 lut_as_logic_used=2468 lut_as_logic_util_percentage=6.02
lut_as_memory_available=13400 lut_as_memory_fixed=0 lut_as_memory_prohibited=0 lut_as_memory_used=172
lut_as_memory_util_percentage=1.28 lut_as_shift_register_fixed=0 lut_as_shift_register_used=76 lut_in_front_of_the_register_is_unused_available=76
lut_in_front_of_the_register_is_unused_fixed=76 lut_in_front_of_the_register_is_unused_prohibited=76 lut_in_front_of_the_register_is_unused_used=659 lut_in_front_of_the_register_is_used_available=659
lut_in_front_of_the_register_is_used_fixed=659 lut_in_front_of_the_register_is_used_prohibited=659 lut_in_front_of_the_register_is_used_used=474 register_driven_from_outside_the_slice_fixed=474
register_driven_from_outside_the_slice_used=1133 register_driven_from_within_the_slice_fixed=1133 register_driven_from_within_the_slice_used=1427 slice_available=10250
slice_fixed=0 slice_prohibited=0 slice_registers_available=82000 slice_registers_fixed=0
slice_registers_prohibited=0 slice_registers_used=2560 slice_registers_util_percentage=3.12 slice_used=914
slice_util_percentage=8.92 slicel_fixed=0 slicel_used=517 slicem_fixed=0
slicem_used=397 unique_control_sets_available=10250 unique_control_sets_fixed=10250 unique_control_sets_prohibited=0
unique_control_sets_used=114 unique_control_sets_util_percentage=1.11 using_o5_and_o6_available=1.11 using_o5_and_o6_fixed=1.11
using_o5_and_o6_prohibited=1.11 using_o5_and_o6_used=44 using_o5_output_only_available=44 using_o5_output_only_fixed=44
using_o5_output_only_prohibited=44 using_o5_output_only_used=8 using_o6_output_only_available=8 using_o6_output_only_fixed=8
using_o6_output_only_prohibited=8 using_o6_output_only_used=24
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_prohibited=0 bscane2_used=1
bscane2_util_percentage=25.00 capturee2_available=1 capturee2_fixed=0 capturee2_prohibited=0
capturee2_used=0 capturee2_util_percentage=0.00 dna_port_available=1 dna_port_fixed=0
dna_port_prohibited=0 dna_port_used=0 dna_port_util_percentage=0.00 efuse_usr_available=1
efuse_usr_fixed=0 efuse_usr_prohibited=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_prohibited=0 frame_ecce2_used=0
frame_ecce2_util_percentage=0.00 icape2_available=2 icape2_fixed=0 icape2_prohibited=0
icape2_used=0 icape2_util_percentage=0.00 pcie_2_1_available=1 pcie_2_1_fixed=0
pcie_2_1_prohibited=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00 startupe2_available=1
startupe2_fixed=0 startupe2_prohibited=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_prohibited=0 xadc_used=0
xadc_util_percentage=0.00

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -debug_log=default::[not_specified] -directive=default::default -fanout_limit=default::10000
-flatten_hierarchy=default::rebuilt -fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified]
-include_dirs=default::[not_specified] -incremental=default::[not_specified] -keep_equivalent_registers=default::[not_specified] -lint=default::[not_specified]
-max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1 -max_uram=default::-1
-max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified] -no_lc=default::[not_specified]
-no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -os=default::[not_specified] -part=xc7k70tfbg676-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=cpu_system_wrapper -verilog_define=default::[not_specified]
usage
elapsed=00:00:42s hls_ip=0 memory_gain=0.000MB memory_peak=1278.762MB