fifo Project Status
Project File:	uart.xise	Parser Errors:	No Errors
Module Name:	fifo	Implementation State:	New
Target Device:	xc3s250e-4tq144	Errors:
Product Version:	ISE 14.6	Warnings:
Design Goal:	Balanced	Routing Results:
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:
Environment:		Final Timing Score:

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report
Translation Report
Map Report
Place and Route Report
Power Report
Post-PAR Static Timing Report
Bitgen Report

 

Secondary Reports			[-]
Report Name	Status	Generated

Date Generated: 04/30/2021 - 04:41:01