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Péter Szántó, András Széll, Béla Fehér: Accelerating SOLiD short read assembly with GPU (download PDF)
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Many-Core and Reconfigurable Supercomputing Conference 2010
22-24. March 2010., Rome, Italy
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Péter Szántó, Béla Fehér, Attila Bérces: Accelerating Virtual Screening of Compound Libraries (download PDF)
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Many-Core and Reconfigurable Supercomputing Conference 2009
March 25th - 26th, 2009, Berlin, Germany
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Péter Szántó, Gábor Szedő, Béla Fehér: High Performance Timing-Driven Rank Filter (download PDF) Péter Szántó, Gábor Szedő, Béla Fehér: High Performance Timing-Driven Rank Filter (download PDF)
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13. IEEE International Conference on Electronics, Circuits and Systems
December 10-13., 2006., Nizza, France
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Péter Szántó, Gábor Szedő, Béla Fehér: Implementing 2D Median Filter in FPGA (download PDF)
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VSB-Technical University of Ostrava, Mechanical Series journal
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Péter Szántó, Gábor Szedő, Béla Fehér: Implementing 2D Median Filter in FPGA (download PDF)
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7. International Carpathian Control Confrence (ICCC 2006)
May 29-31., 2006., Ostrava, Czeh Republic
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Péter Szántó, Béla Fehér: Scalable Rasterizer Unit (download PDF)
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Third Hungarian Conference on Computer Graphics and Geometry
November 17-18., 2005., Budapest, Hungary
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Péter Szántó, Béla Fehér: Exact Bucket Sorting for Segmented Screen Rendering (download PDF)
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GSPx 2005
October 24-27., 2005., Santa Clara, California, USA
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Péter Szántó, János Lazányi, Béla Fehér: Efficient Multi-Channel FIR Filters in FPGA (download PDF)
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International Carpathian Control Conference 2005
May 24-27., 2005., Miskolc-Lillafüred, Hungary
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Péter Szántó: Efficient and Scalable 3D Rendering Architecture (download PDF)
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DATE 2005 EDAA PhD Forum
March 7-11., 2005., Munich, Germany
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Péter Szántó, Béla Fehér: High Performance Visibility Testing with Screen Segmentation (download PDF)
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ESTIMedia 2004 (Workshop on Embedded Systems for Real-Time Multimedia)
September 6-7., 2004., Stockholm, Sweden
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Péter Szántó, Béla Fehér: 3D Rendering using FPGAs (download PDF)
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-VLSI-SOC 2003 - International Conference on Very Large Scale Integration
December 1-3., 2003., Darmstadt, Germany
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Péter Szántó, Béla Fehér: Implementing a Programmable Pixel Pipeline in FPGAs (download PDF)
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Second Hungarian Conference on Computer Graphics and Geometry
June 30.-July 1., 2003., Budapest, Hungary
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