calc_1 Project Status
Project File: TST.xise Parser Errors: No Errors
Module Name: calc_1 Implementation State: Programming File Generated
Target Device: xc3s250e-5tq144
  • Errors:
No Errors
Product Version:ISE 14.6
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of 4 input LUTs 4 4,896 1%  
Number of occupied Slices 4 2,448 1%  
    Number of Slices containing only related logic 4 4 100%  
    Number of Slices containing unrelated logic 0 4 0%  
Total Number of 4 input LUTs 4 4,896 1%  
Number of bonded IOBs 20 108 18%  
Average Fanout of Non-Clock Nets 1.00      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints:      
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSze márc. 30 09:15:40 2022000
Translation ReportCurrentSze márc. 30 09:15:49 2022000
Map ReportCurrentSze márc. 30 09:16:00 2022002 Infos (2 new)
Place and Route ReportCurrentSze márc. 30 09:16:10 2022001 Info (1 new)
Power Report     
Post-PAR Static Timing ReportCurrentSze márc. 30 09:16:14 2022006 Infos (6 new)
Bitgen ReportCurrentSze márc. 30 09:16:19 2022000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentSze márc. 30 09:16:20 2022
WebTalk Log FileCurrentSze márc. 30 09:16:22 2022

Date Generated: 03/30/2022 - 15:22:59