Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.6 (WebPack) - P.68d Target Family: Spartan3E
OS Platform: NT64 Target Device: xc3s250e
Project ID (random number) 4ac46369b20d411386500d6482c86091.13B848A2EBCF4E63B1F95D9E7B020A8E.1 Target Package: tq144
Registration ID __0_0_0 Target Speed: -5
Date Generated 2022-03-30T09:16:20 Tool Flow ISE
 
User Environment
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i7-4702MQ CPU @ 2.20GHz CPU Speed 2195 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Xors=8
  • 1-bit xor2=8
MiscellaneousStatistics
  • AGG_BONDED_IO=20
  • AGG_IO=20
  • AGG_SLICE=4
  • NUM_4_INPUT_LUT=4
  • NUM_BONDED_IBUF=12
  • NUM_BONDED_IOB=8
  • NUM_SLICEL=4
NetStatistics
  • NumNets_Active=36
  • NumNodesOfType_Active_DOUBLE=25
  • NumNodesOfType_Active_DUMMY=8
  • NumNodesOfType_Active_DUMMYESC=12
  • NumNodesOfType_Active_HUNIHEX=22
  • NumNodesOfType_Active_INPUT=16
  • NumNodesOfType_Active_IOBOUTPUT=12
  • NumNodesOfType_Active_OMUX=1
  • NumNodesOfType_Active_OUTPUT=4
  • NumNodesOfType_Active_PREBXBY=1
  • NumNodesOfType_Active_VFULLHEX=3
  • NumNodesOfType_Active_VUNIHEX=15
SiteStatistics
  • IBUF-DIFFMI=1
  • IBUF-DIFFSI=1
  • IOB-DIFFM=4
  • IOB-DIFFS=3
  • SLICEL-SLICEM=3
SiteSummary
  • IBUF=12
  • IBUF_INBUF=12
  • IBUF_PAD=12
  • IOB=8
  • IOB_OUTBUF=8
  • IOB_PAD=8
  • SLICEL=4
  • SLICEL_G=4
 
Configuration Data
IBUF_PAD
  • IOATTRBOX=[LVCMOS25:12]
IOB
  • O1=[O1_INV:0] [O1:8]
IOB_OUTBUF
  • IN=[IN_INV:0] [IN:8]
IOB_PAD
  • DRIVEATTRBOX=[12:8]
  • IOATTRBOX=[LVCMOS25:8]
  • SLEW=[SLOW:8]
 
Pin Data
IBUF
  • I=12
  • PAD=12
IBUF_INBUF
  • IN=12
  • OUT=12
IBUF_PAD
  • PAD=12
IOB
  • O1=8
  • PAD=8
IOB_OUTBUF
  • IN=8
  • OUT=8
IOB_PAD
  • PAD=8
SLICEL
  • G1=4
  • G2=4
  • Y=4
SLICEL_G
  • A1=4
  • A2=4
  • D=4
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-tq144-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s250e-tq144-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 255 255 0 0 0 0 0
bitgen 293 293 0 0 0 0 0
bitinit 4 4 0 0 0 0 0
libgen 1 0 0 0 0 0 0
map 293 292 0 0 0 0 0
ngdbuild 305 304 0 0 0 0 0
par 291 291 0 0 0 0 0
platgen 2 1 0 0 0 0 0
psf2Edward 1 1 0 0 0 0 0
trce 290 290 0 0 0 0 0
xdsgen 1 1 0 0 0 0 0
xps 13 0 0 0 0 0 0
xst 622 621 0 0 0 0 0
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2022-03-30T08:57:40
PROP_intWbtProjectID=13B848A2EBCF4E63B1F95D9E7B020A8E PROP_intWbtProjectIteration=1
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_AutoTop=true PROP_DevFamily=Spartan3E
PROP_DevDevice=xc3s250e PROP_DevFamilyPMName=spartan3e
PROP_DevPackage=tq144 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-5 PROP_PreferredLanguage=Verilog
FILE_UCF=1 FILE_VERILOG=1
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_IBUF=12 NGDBUILD_NUM_LUT2=4 NGDBUILD_NUM_OBUF=8
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_IBUF=12 NGDBUILD_NUM_LUT2=4 NGDBUILD_NUM_OBUF=8
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s250e-5-tq144 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=500 -bufg=24
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5