top_modul Project Status
Project File: TLC5955_control.xise Parser Errors: No Errors
Module Name: top_modul Implementation State: New
Target Device: xc6slx9-2tqg144
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogCurrentCs dec. 10 19:18:28 2015
WebTalk ReportCurrentSzo aug. 15 20:49:34 2015
WebTalk Log FileCurrentSzo aug. 15 20:49:43 2015

Date Generated: 12/10/2015 - 23:16:09