Project Statistics |
PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
PROP_ISimsUseCustomWaveConfigFile_behav=true |
PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
PROP_PropSpecInProjFile=Store all values |
PROP_SelectedInstanceHierarchicalPath=/full_test_topmodul |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=Schematic |
PROP_UseSmartGuide=false |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_intProjectCreationTimestamp=2015-04-15T13:01:50 |
PROP_intWbtProjectID=7DDA5D88A0EC4D90B01F02A1E8B59954 |
PROP_intWbtProjectIteration=31 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_lockPinsUcfFile=changed |
PROP_selectedSimRootSourceNode_behav=work.full_test_topmodul |
PROP_xilxBitgStart_IntDone=true |
PROP_AutoTop=true |
PROP_DevFamily=Spartan6 |
PROP_ISimsUseCustomWaveConfigFilename_behav=changed |
PROP_DevDevice=xc6slx9 |
PROP_DevFamilyPMName=spartan6 |
PROP_ISimSimulationRunTime_behav_tb=30 ms |
PROP_DevPackage=tqg144 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-2 |
PROP_PreferredLanguage=Verilog |
FILE_COREGEN=1 |
FILE_UCF=1 |
FILE_VERILOG=13 |