Static Timing Analysis

Project : ECG_PGA_Filt
Build Time : 09/22/23 16:35:41
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_DelSig_Ext_CP_Clk ADC_DelSig_Ext_CP_Clk 24.000 MHz 24.000 MHz N/A
ADC_DelSig_Ext_CP_Clk(routed) ADC_DelSig_Ext_CP_Clk(routed) 24.000 MHz 24.000 MHz N/A
ClockBlock/aclk_glb_ff_0 ClockBlock/aclk_glb_ff_0 UNKNOWN UNKNOWN N/A
ClockBlock/clk_bus_glb_ff ClockBlock/clk_bus_glb_ff UNKNOWN UNKNOWN N/A
CyILO CyILO 100.000 kHz 100.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
ADC_DelSig_theACLK CyMASTER_CLK 1.043 MHz 1.043 MHz N/A
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
\ADC_DelSig:DSM\/dec_clock \ADC_DelSig:DSM\/dec_clock UNKNOWN UNKNOWN N/A
+ Clock To Output Section
+ ClockBlock/clk_bus_glb_ff
Source Destination Delay (ns)
\I2C_LCD:I2C_FF\/sda_out SDA(0)_PAD:out 23.011
Type Location Fanout Instance/Net Source Dest Delay (ns)
i2ccell F(I2C,0) 1 \I2C_LCD:I2C_FF\ \I2C_LCD:I2C_FF\/clock \I2C_LCD:I2C_FF\/sda_out 1.000
Route 1 \I2C_LCD:sda_x_wire\ \I2C_LCD:I2C_FF\/sda_out SDA(0)/pin_input 7.582
iocell7 P15[1] 1 SDA(0) SDA(0)/pin_input SDA(0)/pad_out 14.429
Route 1 SDA(0)_PAD SDA(0)/pad_out SDA(0)_PAD:out 0.000
Clock Clock path delay 0.000
\I2C_LCD:I2C_FF\/scl_out SCL(0)_PAD:out 19.599
Type Location Fanout Instance/Net Source Dest Delay (ns)
i2ccell F(I2C,0) 1 \I2C_LCD:I2C_FF\ \I2C_LCD:I2C_FF\/clock \I2C_LCD:I2C_FF\/scl_out 1.000
Route 1 \I2C_LCD:Net_643_0\ \I2C_LCD:I2C_FF\/scl_out SCL(0)/pin_input 2.674
iocell8 P15[5] 1 SCL(0) SCL(0)/pin_input SCL(0)/pad_out 15.925
Route 1 SCL(0)_PAD SCL(0)/pad_out SCL(0)_PAD:out 0.000
Clock Clock path delay 0.000